MT Configuration Register
| ENABLE_BLERD | This register bit needs to be set to enable CYBLERD55 1’b1 - CYBLERD55 enabled 1’b0 - CYBLERD55 disabled On power up this bit needs to be set to make CYBLERD55 active. |
| DEEPSLEEP_EXIT_CFG | This register bit indicates the source for PSoC DeepSleep exit to BLESS 1’b0 - act_power_good from SRSS indicates PSoC DeepSleep exit 1’b1 - MT_CFG.DEEPSLEEP_EXITED indicates PSoC DeepSleep exit |
| DEEPSLEEP_EXITED | This register bit is used by FW to indicate that PSoC is out of DeepSleep 1’b0 - PSoC in DeepSleep 1’b1 - PSoC out of DeepSleep This bit is cleared by HW on exit from DPSLP |
| ACT_LDO_NOT_BUCK | This register bit specifies whether the Active LDO or BUCK in CYBLERD55 is used in active mode |
| OVERRIDE_HVLDO_BYPASS | This register should be set to override the HW generated signal to HVLDO. When set HVLDO_BYPASS is driven to the IP |
| HVLDO_BYPASS | Override value for HVLDO BYPASS 1’b0: bypass the HVLDO 1’b1: Do not bypass the HVLDO |
| OVERRIDE_ACT_REGULATOR | This register should be set to override the HW generated signal to enable ACTIVE_LDO/BUCK. When set ACT_REGULATOR_EN is driven to CYBLERD55 |
| ACT_REGULATOR_EN | Override value for ACT_LDO_EN/BUCK_EN |
| OVERRIDE_DIG_REGULATOR | This register should be set to override the HW generated signal to Digital regulator of CYBLERD55. When set DIG_REGULATOR_EN is driven to CYBLERD55 |
| DIG_REGULATOR_EN | Override value for digital regulator of CYBLERD55 |
| OVERRIDE_RET_SWITCH | This register should be set to override the HW generated signal to the retention switch of CYBLERD55. When set OVERRIDE_RET_SWITCH is driven to the IP |
| RET_SWITCH | Override value for RET_SWITCH |
| OVERRIDE_ISOLATE | This register should be set to override the HW generated isolation signal to CYBLERD55. When set ISOLATE_N is driven to the IP |
| ISOLATE_N | Override value for isolation to CYBLERD55 |
| OVERRIDE_LL_CLK_EN | This register should be set to override the HW generated ECO Clock gate. When set LL_CLK_EN is used to gate the clock |
| LL_CLK_EN | Override value for LL Clock gate |
| OVERRIDE_HVLDO_EN | This register should be set to override the HW generated enable to HVLSO. When set HVLDO_EN is used. |
| HVLDO_EN | Overrie value for HVLDO enable 1’b1: switch to Active LDO 1’b0: switch to standby LDO |
| DPSLP_ECO_ON | This bit when set indicates that ECO clock should be kept on even in BLESS DPSLP. This bit must be toggled only when the Link Layer is active. |
| OVERRIDE_RESET_N | This register should be set to override the HW generated reset to CYBLERD55. When set RESET_N is used. |
| RESET_N | Overrie value for CYBLERD55 RESET_N |
| OVERRIDE_XTAL_EN | This register should be set to override the HW generated XTAL_EN to CYBLERD55. When set XTAL_EN is used. |
| XTAL_EN | Overrie value for CYBLERD55 XTAL_EN |
| OVERRIDE_CLK_EN | This register should be set to override the HW generated CLK_EN to CYBLERD55. When set CLK_EN is used. |
| BLERD_CLK_EN | Overrie value for CYBLERD55 CLK_EN |
| OVERRIDE_RET_LDO_OL | This register should be set to override the HW generated RET_LDO_OL_HV to CYBLERD55. When set CLK_EN is used. |
| RET_LDO_OL | Overrie value for CYBLERD55 RET_LDO_OL_HV |
| HVLDO_POR_HV | Reset for HVLDO 1’b1 - HVLDO Disabled 1’b0 - HVLDO Enabled |